Hardware Accelerators for High Efficiency Video Coding in Surveillance and Video Conference Applications
Mohammed Sharaf Sayed
The H.265/HEVC (High Efficiency Video Coding) standard added huge computational complexity to achieve double the compression ratio (i.e. 50% bit rate reduction) for the same video quality in comparison with the preceding H.264/AVC standard. This high computational cost presents a big challenge for real-time compression of video data. Special attention should be given to surveillance and video conference applications due to their importance. In such applications, real-time processing and low latency are not privilege but a must.
Existing complete hardware solutions lack flexibility, especially that there is no single solution that can fit perfectly all video coding applications. Software implementation with hardware accelerators can achieve the required flexibility and meets the high processing load in the HEVC encoder. In addition, surveillance and video conference applications have unique characteristics that can be exploited to reduce the tremendous processing load in the HEVC encoder.
Dr. Mohammed Sharaf Sayed is an Associate Professor in the ECE department, Egypt-Japan University of Science and Technology. His research interests include Digital Systems Design, System-on-Chip, Video Coding, Embedded Vision Systems, and Wireless Body Area Networks.
Dr. Sayed received several awards both in Canada and in Egypt. He has one US patent and seven contributions to the ITU/MPEG video coding standards, two of them included in the H.264 standard’s reference hardware model. He authored and co-authored more than 80 international publications. Dr. Sayed managed and participated in several national/international research and development projects. He acted as a reviewer for several IEEE transactions and other journals.