Home


July 9, 2018

Open Campus Day at E-JUST

Al-Fajr Electronic Website Monday July 9th, 2018   On July 6-7th, 2018, Egypt-Japan University of Science and Technology (E-JUST) organized...
Read More
June 21, 2018

H.E. Abd El-Ghaffar Visits E-JUST Headquarters

Educational Gate Electronic Website Thursday June 21st, 2018 On Thursday June 21st, 2018, Minister of Higher Education and Scientific Research...
Read More
June 16, 2018

E-JUST Wins 3 Science and Technology State Awards and Ranks Fourth Among Egyptian Universities

Egypt-Japan University of Science and Technology (E-JUST) won fourth place among the ranking of Egyptian Universities. E-JUST won three state...
Read More


Oct
20
Sat
EJUST Graduate Programs Promotion Event @ Cairo office
Oct 20 @ 10:00 am
Oct
21
Sun
AlZahraa American School Visit EJUST @ EJUST HQ
Oct 21 @ 10:00 am
Public Seminar Challenges of living in space @ EJUST HQ
Oct 21 @ 1:00 pm – 2:00 pm
Oct
31
Wed
16th Research Seminar “Software Cache Coherent Control by Parallelizing Compiler” @ E-JUST, HQ Building - Room No. 207
Oct 31 @ 1:00 pm – 2:00 pm

Abstract:

Multicore technology enables development of hundreds or thousands core processor on a single chip.
However, on such multicore processors, cache coherence hardware will become very complex, hot and expensive.
This talk introduces a parallelizing compiler directed software coherence scheme for shared memory multicore systems without hardware cache coherence control. The general idea of the proposed method is that an automatic parallelizing compiler parallelize coarse grain task, analyzes stale data and line sharing in the program, then solves those problems by simple program restructuring and data synchronization.

The proposed method is a simple and efficient software cache coherent control scheme built on OSCAR automatic parallelizing compiler and evaluated on Renesas RP2 with 8 SH-4A cores processor. Performance evaluation was performed using 10 benchmark programs from SPEC2000, SPEC2006, NAS Parallel Benchmark (NPB) and Media Bench II. The proposed method performed as same as or better than hardware cache coherence scheme
while still provided correct result as the hardware coherent mechanism. For example, the proposed software cache coherent control (NCC) gave us 2.63 times speedup for SPEC 2000 quake with 4 cores against sequential execution while got only 2.52 times speedup for 4 cores MESI hardware coherent control. Also, the software coherence control gave us 4.37 speed up for 8 cores with no hardware coherent mechanism available.

Bio:

Keiji Kimura received the B.S., M.S. and Ph. D degrees in electrical engineering from Waseda University in 1996, 1998, 2001, respectively. He was an assistant professor in 2004, associate professor of Department of Computer Science and Engineering in 2005, and professor in 2012 at Waseda University. He was also a department head of CSE from 2015 to 2016 and an assistant dean of FSE from 2016 to 2017. He is a recipient of 2014 MEXT (Ministry of Education, Culture, Sports, Science and Technology in Japan) award. His research interest includes microprocessor architecture, multiprocessor architecture, multicore processor architecture, and there compiler. He is a member of IPSJ, ACM and IEEE. He has served on program committee of conferences such as ICCD, ICPADS, ICPP, LCPC, IISWC, ICS, IPDPS, and PACT.

Dec
2
Sun
18th BoT meeting @ Cairo office
Dec 2 – Dec 3 all-day
Dec
16
Sun
International Japan-Africa Conference on Electronics, Communications and Computations (JAC-ECC) 2018 Alexandria, Egypt @ EJUST HQ
Dec 16 – Dec 18 all-day