June 11, 2018

E-JUST Iftar Gathering

On Monday June 11th, 2018, Egypt-Japan University of Science and Technology (E-JUST) organized an Iftar Gathering to E-JUST family members....
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June 1, 2018

“Higher Education”: 18 Thousand International Publications in 2017.. Cairo University Tops the List

Egyptian Science, Technology and Innovation Observatory announced the published research papers for international Egyptian researchers. The research papers reached 18722...
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May 14, 2018

Minister of Higher Education Heads E-JUST 17th BoT Meeting

On Monday May 14th, 2018 H.E. Minister of Higher Education and Scientific Research (MHESR), heads Egypt-Japan University of Science and...
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EJUST Graduate Programs Promotion Event @ Cairo office
Oct 20 @ 10:00 am
AlZahraa American School Visit EJUST @ EJUST HQ
Oct 21 @ 10:00 am
Public Seminar Challenges of living in space @ EJUST HQ
Oct 21 @ 1:00 pm – 2:00 pm
16th Research Seminar “Software Cache Coherent Control by Parallelizing Compiler” @ E-JUST, HQ Building - Room No. 207
Oct 31 @ 1:00 pm – 2:00 pm


Multicore technology enables development of hundreds or thousands core processor on a single chip.
However, on such multicore processors, cache coherence hardware will become very complex, hot and expensive.
This talk introduces a parallelizing compiler directed software coherence scheme for shared memory multicore systems without hardware cache coherence control. The general idea of the proposed method is that an automatic parallelizing compiler parallelize coarse grain task, analyzes stale data and line sharing in the program, then solves those problems by simple program restructuring and data synchronization.

The proposed method is a simple and efficient software cache coherent control scheme built on OSCAR automatic parallelizing compiler and evaluated on Renesas RP2 with 8 SH-4A cores processor. Performance evaluation was performed using 10 benchmark programs from SPEC2000, SPEC2006, NAS Parallel Benchmark (NPB) and Media Bench II. The proposed method performed as same as or better than hardware cache coherence scheme
while still provided correct result as the hardware coherent mechanism. For example, the proposed software cache coherent control (NCC) gave us 2.63 times speedup for SPEC 2000 quake with 4 cores against sequential execution while got only 2.52 times speedup for 4 cores MESI hardware coherent control. Also, the software coherence control gave us 4.37 speed up for 8 cores with no hardware coherent mechanism available.


Keiji Kimura received the B.S., M.S. and Ph. D degrees in electrical engineering from Waseda University in 1996, 1998, 2001, respectively. He was an assistant professor in 2004, associate professor of Department of Computer Science and Engineering in 2005, and professor in 2012 at Waseda University. He was also a department head of CSE from 2015 to 2016 and an assistant dean of FSE from 2016 to 2017. He is a recipient of 2014 MEXT (Ministry of Education, Culture, Sports, Science and Technology in Japan) award. His research interest includes microprocessor architecture, multiprocessor architecture, multicore processor architecture, and there compiler. He is a member of IPSJ, ACM and IEEE. He has served on program committee of conferences such as ICCD, ICPADS, ICPP, LCPC, IISWC, ICS, IPDPS, and PACT.

18th BoT meeting @ Cairo office
Dec 2 – Dec 3 all-day
International Japan-Africa Conference on Electronics, Communications and Computations (JAC-ECC) 2018 Alexandria, Egypt @ EJUST HQ
Dec 16 – Dec 18 all-day